The present invention relates to semiconductor devices and methods of fabricating the same and, more particularly, to an electrically erasable and programmable read-only memory (EEPROM) device and methods of fabricating the same.
In a semiconductor device, EEPROM cells have the non-volatile characteristic of being able to retain their stored data even though their power supplies are interrupted. Typically, each of the EEPROM cells has a floating gate acting as a data storage. The floating gate is electrically isolated and stores charges therein. The data of an EEPROM cell is classified into logic “1” and logic “0” according to the amount of the charges stored in the floating gate.
FIG. 1A and FIG. 1B are a plan view and a cross-sectional view for illustrating the configuration of a conventional EEPROM.
As illustrated in FIG. 1A and FIG. 1B, a device isolation layer 15 is disposed to define an active region A in a predetermined region of a semiconductor substrate 10. A control gate CG and a selection gates SG are disposed on the active region A and the device isolation layer 15 to act as a control gate electrode of a memory transistor and a gate electrode of a selection transistor, respectively. A floating gate FG is interposed between the control gate CG and the active region A to act as a charge storage layer. An intergate dielectric 50 is interposed between the floating gate FG and the control gate CG to electrically isolate the floating gate FG.
A gate oxide layer 30 and a tunnel oxide layer 20 are interposed between the floating gate FG and the active region A. The tunnel oxide layer 20 is surrounded by the gate oxide layer 30, as illustrated in FIG. 1A, and is thinner than the gate oxide layer 30, as illustrated in FIG. 1B.
In addition, a lower conductive pattern 60 electrically connected to the selection gates SG is interposed between the selection gates SG and the active region A. For this, the intergate dielectric 50 is not formed between the selection gates SG and the lower conductive pattern 60. Rather, the gate oxide layer 30 is interposed between the lower conductive pattern 60 and the active region A.
A tunnel impurity region 40 is interposed between the control gate CG and the selection gates SG. The tunnel impurity region 40 extends downwardly toward the tunnel oxide layer 20. A source region S spaced apart from the tunnel impurity region 40 is disposed at one side of the control gate CG, and a drain region D spaced apart from the tunnel impurity region 40 is disposed at one side of the selection gates SG.
According to conventional methods for forming an EEPROM, a control gate CG and a floating gate FG are formed using a self-aligned etch process. In order to prevent the tunnel oxide layer 20 from being damaged by misalignment during the self-aligned etch process, the floating gate FG has a margin of a predetermined width W from the edge of the tunnel oxide layer 20. Considering that damage to the tunnel oxide layer 20 has an effect on the characteristics of an EEPROM, a space margin should be provided between the floating gate FG and the tunnel oxide layer 20. However, space margins cause difficulty in developing higher-integrated EEPROM.